The present invention relates to a method and/or architecture for bus arbitration generally and, more particularly, to bus arbitration when all masters are unable to use the bus.
An Advanced Microcontroller Bus Architecture (AMBA) specification defines on-chip communications standards for microcontrollers. The AMBA specification is being used worldwide by a variety of application specific integrated circuit vendors. The AMBA is being used in wireless, telecommunications, networking, office automation, and storage applications. The AMBA specification defines three busses, an Advanced High-Performance Bus (AHB), an Advanced System Bus (ASB), and an Advanced Peripheral Bus (APB).
The AHB portion of the AMBA specification provides communications between multiple masters and multiple slaves via the AHB. A bus mastership for the AHB (the bus) is controlled by an arbiter. When a given master has the bus mastership, then the given master may initiate one or more transfers with one or more slaves. Any slave that cannot respond immediately to a transfer may issue a RETRY or a SPLIT response. The RETRY and the SPLIT responses allow the bus to be used for other purposes while the slave prepares the transfer. The given master may lock the bus mastership (i.e., a locked master) to retain control of the bus until the slave completes the transfer.
The arbiter must grant the bus mastership to a default master if a particular situation exists where none of the masters are able to use the bus (i.e., a no-master situation). The default master may be a preselected master, any master that would benefit from having a low access latency to the bus, or the locked master. The default master must have sufficient complexity to perform only IDLE transfers under the no-master situation.
Four conditions may exist in which give rise to the no-master situation. A first condition occurs when none of the masters require use of the bus and none of the masters are involved in a SPLIT transaction. A second condition where no master is able to use the bus occurs when all masters are waiting on slaves that have issued the SPLIT response. A third condition occurs when one or more masters are involved in the SPLIT response and no other master is requesting the bus mastership. Under the first, second and third conditions, the arbiter must grant the bus mastership to the preselected master or any master than may benefit from having a low access latency to the bus. A fourth condition occurs when the locked master has received the SPLIT response. Under the fourth condition, the arbiter cannot allow a different master from corrupting the locked master""s lock transfer. Therefore, the arbiter must grant the bus mastership to a master that will only drive IDLE transfers during this time.
Several approaches have been proposed to simplify the no-master situation where none of the masters are able to use the bus. A first approach creates a dedicated default master that only performs IDLE transfers. The first approach is straightforward but also consumes one of the sixteen master positions available on the bus. A second approach is to modify the slaves to ignore or queue transfers under the no-master situation. The second approach deviates from the AMBA specification and thus may not coexist with AMBA-compliant masters and slaves. Furthermore, a queuing mechanism for the modified slaves to handle repeated requests from the modified masters is complicated. A third approach is to restrict transfers on the bus so that the no-master situation cannot take place. The third approach requires careful planning by design personnel. The third approach leaves room for design mistakes that can cause problems with the bus.
The present invention concerns a system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus and the at least one master. The at least one master may be configured to present at least one transfer signal. The first circuit may be configured to (i) grant a bus mastership to a first master of the at least one master, (ii) present a first transfer signal of the at least one transfer signal to the bus in response to granting the bus mastership to the first master, (iii) remove the bus mastership from all masters of the at least one master, and (iv) present an idle transfer signal to the bus in response to removing the bus mastership from all masters.
The objects, features and advantages of the present invention include providing a method and/or architecture for bus arbitration generally and, more particularly, to bus arbitration when all masters are unable to use the bus that may (i) require minor additional logic for the bus and the arbiter, (ii) provides for a maximum number of masters allowed on the bus, (iii) requires no specification deviations for the masters and the slaves, and/or (iv) ensures that third party masters and slaves will work on the bus.